This application claims priority from Korean Patent Application No. 10-2004-0061955 filed on Aug. 6, 2004, which we incorporate by reference.
1. Field of the Invention
The field of the invention relates to a digital-to-analog conversion device and, more particularly, to a fixed offset digital-to-analog conversion device and method.
2. Description of the Related Art
A digital-to-analog conversion (DAC) device converts a digital input signal into an analog signal with a voltage level corresponding to the digital input signal. The converted analog signal may be used in various semiconductor devices performing digital to analog conversion. An example of a conventional DAC is disclosed in U.S. Pat. No. 5,212,482, titled Digital-To-Analog Converter Having An Externally Selectable Output Voltage Range, issued Mar. 18, 1993 to Tetsuo Okuyama.
FIG. 1 is a circuit diagram of a conventional DAC 10. Referring to FIG. 1, the DAC 10 includes an input voltage generating circuit 11 and operational amplifiers (OP AMPs) 12 and 13. The input voltage generating circuit 11 includes a plurality of NMOS transistors NM1 through NM9. The input voltage generating circuit 11 generates input voltages Vin and Vinb on output nodes D1 and D2 in response to digital code signals B0 through B2 and B0B through B2B, respectively. The OP AMPs 12 and 13 generate output voltages Vout and Voutb, respectively, in response to the input voltages Vin and Vinb, respectively, and a reference voltage Vref. The OP AMP 12 supplies a current I1 to the input voltage generating circuit 11 via a resistor R0. The OP AMP 13 supplies a current I2 to the input voltage generating circuit 11 via a resistor R1. Resistors R0 and R1 may form a feedback loop corresponding to OP AMPs 12 and 13, respectively. The OP AMPs 12 and 13 have input offset voltages Vos1 and Vos2, respectively, where the input offset voltages Vos1 and Vos2 may be determined according to Equation 1.
                                          Vos            ⁢                                                  ⁢            1                    =                                    I              ⁢                                                          ⁢              1                                      G              ⁢                                                          ⁢              1                                      ⁢                                  ⁢                              Vos            ⁢                                                  ⁢            2                    =                                    I              ⁢                                                          ⁢              2                                      G              ⁢                                                          ⁢              2                                                          Equation        ⁢                                  ⁢        1            
As shown in Equation 1, the input offset voltages Vos1 and Vos2 are proportional to the currents I1 and I2, respectively, and inversely proportional to the gain G1 of the OP AMP 12, and the gain G2 of the OP AMP 13. Since the input offset voltages Vos1 and Vos2 act as offsets (errors) of the output voltages Vout and Voutb, when the input offset voltages Vos1 and Vos2 increase, the offsets of the output voltages Vout and Voutb also increase.
The magnitude of the currents I1 and I2 supplied by OP AMPs 12 and 13, respectively, varies according to the digital code signals B0 through B2 and B0B through B2B input to the input voltage generating circuit 11. Specifically, when the number of NMOS transistors turned on in response to the digital code signals B0 through B2 increases, the magnitude of current I1 increases. Likewise, when the number of NMOS transistors turned on in response to the digital code signals B0B through B2B increases, the magnitude of current I2 increases. Since the magnitude of current OP AMPs 12 and 13 can supply to the input voltage generating circuit 11 is limited, the situation may arise when the OP AMPs 12 and 13 cannot sufficiently supply currents I1 and I2 to the input voltage generating circuit 11. Accordingly, the input voltage generating circuit 11 may generate the input voltages Vin and Vinb that do not correspond to the digital code signals B0 through B2 and B0B through B2B, causing the offsets of the output voltages Vout and Voutb to increase. Thus, in conventional DAC 10, the offsets of the output voltages Vout and Voutb change with changes to the digital code signals B0 through B2 and B0B through B2B.